The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
To provide multiple integrated circuits into a compact device, such as a cell phone, PDA, GPS, or laptop computer, fabricating an integrated circuit structure having a three-dimensional (“3D”) integrated circuit stack or “chip stack” has recently been investigated. A 3D chip stack allows designers or assemblers greater flexibility to stack various chip technologies into small, high performance functional blocks. For example, flash memories combined with static random access memory (SRAM), dynamic random access memory (DRAM), digital signal processors (DSP), or microprocessors are all candidates for this 3D chip stack technique. It may even be possible stack silicon-based chips with Periodic Table group III-V material compound chips, which cannot be easily fabricated monolithically.
3D chip stacks may need to include a cooling mechanism. When two chips are bonded together, one side of each chip is exposed to the air, which can be cooled by the ambient cool air. However, when more chips are bonded together, such as in a 3D chip stack, chips in the middle are not exposed to ambient air. Lack of exposure to ambient air for middle chips may not be a problem for chips that consume less power. For example, memory chips generally consume less power than high-speed central processing unit (CPU) chips, and therefore, memory chips generate less heat, than CPU chips. Therefore, a separate cooling mechanism would not necessarily be required for a 3D memory chip stack. For high-speed CPU chips, however, which consume more power, and therefore generate more heat, a separate cooling mechanism may be necessary for a 3D CPU chip stack.
Accordingly, it is desirable to provide improved integrated circuit structures and methods for fabricating integrated circuits that are able to efficiently dissipate heat generated as a result of power consumption. Additionally, it is desirable to provide three-dimensional integrated circuit structures methods for fabricating such integrated circuit structures with a cooling mechanism for eliminating heat generated at portions thereof that are not exposed to ambient cool air. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.